1. Field of the Invention:
The present invention relates to a MOS static memory device with a read/write circuit.
2. Description of the Related Art:
As the capacity of a static random access memory (SRAM) has been increased from 1 Megabit to 4 Mbits and further to 16 Mbits in recent years, the chip size has been made larger. Accordingly, longer wirings are required for transmitting data, and hence it takes a longer time to transmit data. In order to shorten the data transmission time, such a large-capacity SRAM has been provided with local sense amplifiers disposed in the vicinity of a memory array. Each local sense amplifier amplifies a signal and outputs the amplified signal to the external circuitry. An example of such an SRAM is described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 5, OCTOBER 1990, pp. 1075-1081, "A 23-ns 4-Mb CMOS SRAM with 0.2-.mu.A Standby Current" (hereinafter referred to as Reference 1). In Reference 1, local sense amplifiers each consisting of 16 transistors are located in the vicinity of the memory array.
On the other hand, the information stored in memory cells tends to be destroyed because of a decrease in operating voltage of the SRAM and because of the increase of interference between bit lines due to the floating capacitance in association with an increase in capacity (hereinafter such phenomenon is referred to as a memory destruction). As a counter-measure against memory destruction, Japanese Laid-Open Patent Publication No. 63-128662 (hereinafter referred to as Reference 2) discloses an example in which a small potential difference appearing on bit lines is reproduced by a flip-flop type sense amplifier and the data is rewritten, so that data destruction is prevented. The sense amplifier used in Reference 2 consists of only six transistors,
However, in the above-mentioned method applied to the conventional memory device in which sense amplifiers are disposed at local positions, the sense amplifiers are disposed on each side of the memory array. This method necessarily requires a large chip area.
For example, FIG. 1 schematically shows the construction of a 4-Mbits SRAM chip 100 in Reference 1. The memory cell array of the SRAM chip 100 is divided into 64 sub-arrays. Each sub-array is composed of 1024 rows and 64 columns. Each of areas 101 and 102 in FIG. 1 includes two sub-arrays. Area 103 includes a word decoder for the four sub-arrays existing in the areas 101 and 102. Area 104 along one longer side of the SRAM chip 100 includes a column decoder. Area 105 which is adjacent to the area 104 (i.e., adjacent to the column decoder) includes local sense amplifiers. The area 105 in which the local sense amplifiers are provided necessitates a relatively large area. Specifically, the area 105 occupies about 4% of the entire area of the SRAM chip 100.
On the other hand, the flip-flop type sense amplifier used in Reference 2 is composed of the six transistor elements, and moreover, two of them can be combined into one unit. Therefore, in terms of the area to be required, Reference 2 is considerably advantageous as compared to the SRAM chip 100 in Reference 1. However, if the bit-line potential is reproduced by the flip-flop type sense amplifier as disclosed in Reference 2, the potential of the bit line is changed in a possible full-scale (referred to as "being fullswung"). As a result, a very large current for charge and discharge flows through the bit line. The current I is expressed as follows: EQU I=C.times.V.times.F.times.N . . . (1)
where C denotes a capacitance of a bit line, F denotes the number of times of charge and discharge per second, i.e., the operating frequency, V denotes an amount of voltage change of the bit line, and N denotes the number of bit-line pairs which synchronously operate.
For example, when C=3 pF, V=3.3 V, F=10 MHz, and N=128, the current I is estimated to be 12.7 mA. That is, a large current flows through the bit lines.